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SwitchStarTM ATM Cell Based 1.2Gbps non-blocking Integrated Switch Controller
Features
Single chip controller for IDT77V400 Switching Memory One IDT77V500 and one IDT77V400 form the core required for a 1.2Gbps 8 x 8 port non-blocking switch x Supports up to 8192 Virtual Connections (VCs) x Per VC queuing for fairness, with four priorities per VC available for each output port of the switch x Capable of supporting CBR, VBR, UBR, and ABR (EFCI) service classes x Low power dissipation - 430mW (typ.) x Optional header modification operation x Multicasting and Broadcasting capability x Provides congestion management support through EFCI, CLP, and EPD functionality x System clock cycle times as fast as 25ns (40MHz) x Option available for resolving contention issues between multiple IDT77V500 configurations
x x x
IDT77V500
x x x
One IDT77V500 can manage up to eight IDT77V400's without derating for larger switch configurations Industrial temperature range (-40 C to +85 C) is available Single +3.3V 300mV power supply Available in a 100-pin Thin Plastic Quad Flat Pack (TQFP) and 144-ball BGA
Description
The IDT77V500 ATM Cell Based Switch Controller, when paired with the IDT77V400 Switching Memory, forms the core control logic and switch fabric for a 1.2Gbps non-blocking ATM switch. The IDT77V500 manages all of the switch traffic moving through the IDT77V400, commanding the storage of incoming ATM cells and interpreting and modifying the cell header information as necessary for data flow through the switch. It then uses the header information, including priority indicators, to queue and direct the individual cells for transmission out the appropriate output port of the IDT77V400.
Typical 8 x 8 Switch Configuration using the IDT77V500 Switch Controller
External Interface for Global Setup and Control
8-bit Processor// Call Setup Manager or IDT77V550
Data
IDT77V500
Control
Switch Controller
Data
Control Port 0
155Mbps PHY
Port 0
155Mbps PHY
IDT77V400 Switching Memory 155Mbps PHY
Port 7 Port 7
155Mbps PHY
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SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
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DSC 3607/5
IDT77V500
The IDT77V500 utilizes Per Virtual Connection (VC) Queuing to keep track of each call, and has the capacity to keep track of as many as 8192 individual VC queues. There are four possible priorities available for each of the assigned outputs of the Switching Memory, and CBR, VBR, UBR, and ABR-EFCI service classes are supported by the Switch Controller. Multicasting and broadcasting services are provided, requiring only the appropriate header information to execute these operations automatically without requiring multiple Switching Memory entries. The IDT77V500 also has a mode for managing and transmitting packetized data, enabling easy transition between packet oriented networks such as Ethernet and FDDI and ATM cell oriented networks. The IDT77V500 has an 8-bit Manager Bus interface, MDATA0-7, to a Call Setup Manager processor for the configuration activity and call
setup operation. When a Call Setup Cell is received by the IDT77V400, the cell is directed to a specified output port and the payload processed by the Call Setup Manager. The new Virtual Connection (VC) is then established in the Queue Manager of the IDT77V500, with all operations executed across the 8-bit Manager Bus. Subsequent cells of that particular VC are then prioritized and directed by the Switch Controller as they are received by the IDT77V400; no further interaction with the Call Manager processor is required for ongoing queue and cell management. The IDT77V500 supports a major subset of the available commands and configurations of the IDT77V400 Switching Memory. Please refer to the SwitchStar User Manual for additional feature details and implementation information. The IDT77V500 is fully 3.3V LVTTL compatible, and is packaged in an 100-pin Thin Plastic Quad Flatpack (TQFP) and an 144-ball BGA.
Functional Block Diagram
MD/C MR/W MSTRB MDATA0-7 Call Setup Manager State Machine
OFRM0-7 CBRCLK2 CBRCLK3
Output Service and Arbitration
SFRM Queue Manager
2
SCLK RESETI
Control Logic
SCLK1 Reset1
Output Queues and Link Registers RESETO
2
Switching Memory Interface
32
6
IOD0-31
1 2
CMD0-5
2
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CRCERR
SCLK and Reset are inputs to all blocks. Outputs are always enabled (active).
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IDT77V500
Package Diagrams
All Vcc pins must be connected to power supply. All Vss pins must be connected to ground supply.
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
MDATA7 MD/C MR/W MSTRB NC NC CMD5 CMD4 CMD3 VSS VCC CMD2 CMD1 CMD0 NC NC RESETI SCLK RESETO CBRCLK2 NC CBRCLK3 NC SFRM OFRM7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NC NC MDATA6 MDATA5 MDATA4 VSS VCC MDATA3 MDATA2 MDATA1 MDATA0 VCC VCC VCC CRCERR IOD0 IOD1 IOD2 IOD3 VCC VSS IOD4 IOD5 IOD6 NC
75 74 73 72 71 70 69 68 67
IDT77V500PF PN100-11 100-Pin TQFP Top View2
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC IOD7 IOD8 IOD9 IOD10 IOD11 VCC VSS IOD12 IOD13 IOD14 IOD15 IOD16 IOD17 IOD18 IOD19 VCC VSS IOD20 IOD21 IOD22 IOD23 NC NC ,
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1
2This text
This package code is used to reference the package diagram. does not indicate orientation of the actual part marking.
NC NC OFRM6 OFRM5 VSS VCC OFRM4 OFRM3 OFRM2 OFRM1 OFRM0 VSS VSS VSS IOD31 IOD30 IOD29 IOD28 VSS VCC IOD27 IOD26 IOD25 IOD24 NC
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IDT77V500
BGA Package Diagram
1 A B C D E F G H J K L M VCC VSS NC NC NC NC VCC IOD31 IOD29 NC NC NC 1 2 NC OFRM2 NC NC NC NC VSS IOD30 NC IOD26 NC NC 2 3 OFRM4 OFRM3 NC NC NC VSS NC NC VSS IOD25 IOD22 IOD23 3 4 OFRM7 NC OFRM5 OFRM1 NC VSS NC IOD27 IOD24 IOD20 VSS IOD21 4 5 CBRCLK2 6 SCLK 7 NC RESETI NC NC 8 VCC VSS CMD1 CMD0 NC VCC VCC VCC IOD6 VSS IOD10 IOD11 8 9 CMD4 CMD5 CMD3 NC NC MDATA2 NC NC NC VCC IOD7 IOD9 9 10 NC MSTRB MR/W NC MDATA3 MDATA0 NC NC IOD0 IOD3 NC NC 10 11 MDATA7 MD/C MDATA5 VSS MDATA1 NC NC NC NC IOD2 VSS NC 11 12 NC MDATA6 NC MDATA4 NC NC NC NC IOD1 NC IOD4 IOD5 12 A B C D E F G H J K L M
CBRCLK3 RESETO SFRM OFRM6 OFRM0 NC IOD28 VCC IOD17 NC NC IOD18 5 NC NC VCC NC IOD19 IOD12 IOD14 IOD15 NC IOD16 6
NC CMD2 CRCERR IOD8 VCC IOD13 NC NC 7
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IDT77V500
TQFP Pin Description
Pin Number 18 22,20 Symbol SCLK CBRCLK3, CBRCLK2 I I Type Description System clock: Reference clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchronous signals are referenced to the rising edge of SCLK. CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized. These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less. Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occurred in the cell header. Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation. MD/C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the IDT77V500. Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously. Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read operation (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode) the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the MD/C input) are available to be read on MDATA0-7. Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the IDT77V500. Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain. RESETO will remain HIGH until a START command is received from the Call Setup Manager. Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory are output by the IDT77V500 on this 6-bit bus. Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus. The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s. Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for transfer of the header bytes, configuration register, error and status registers, and the cell memory address between the IDT77V500 and the IDT77V400 Switching Memory. Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bidirectional bus. MD/C, MR/W, and MSTRB determine the mode and data type transferred across the MDATA bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for read operations. Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7 are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0). Power Supply (+3.3V 300mV) Ground No Connect
86
CRCERR
I
2
MD/C
I
3
MR/W
I
4
MSTRB
I
17 19
RESETI RESETO
I O
7-9, 12-14 24
CMD0-5 SFRM
O O I/O
40-43, 46-49, 53-56, 59-66, IOD0-31 69-73, 77-79, 82-85 1, 90-93, 96-98 MDATA0-7
I/O
25, 28-29, 32-35, 36
OFRM1-7 OFRM0 VCC VSS NC
I/O
11, 31, 45, 58, 68, 81, 8789, 94 10, 30, 37-39, 44, 57, 67, 80, 95 5-6, 15-16, 21, 23, 26-27, 50-52, 74-76, 99-100
Power Power ____
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IDT77V500
BGA Pin Description
Pin Number A6 B5, A5 Symbol SCLK CBRCLK3, CBRCLK2 CRCERR I I Type Description System clock: Reference clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchronous signals are referenced to the rising edge of SCLK. CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized. These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less. Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occurred in the cell header. Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation. MD/C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the IDT77V500. Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously. Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read operation (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode) the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the MD/C input) are available to be read on MDATA0-7. Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the IDT77V500. Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain. RESETO will remain HIGH until a START command is received from the Call Setup Manager. Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory are output by the IDT77V500 on this 6-bit bus. Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus. The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s. Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for transfer of the header bytes, configuration register, error and status registers, and the cell memory address between the IDT77V500 and the IDT77V400 Switching Memory.
G7
I
B11
MD/C
I
C10
MR/W
I
B10
MSTRB
I
B7 B6
RESETI RESETO
I O
D8, C8, F7, C9, A9, B9 C5
CMD0-5 SFRM
O O I/O
J10, J12, K11, K10, L12, IOD0-31 M12, J8, L9, H7, M9, L8, M8, H6, K7, J6, K6, M6, J5, M5, G6, K4, M4, L3, M3, J4, K3, K2, H4, G5, J1, H2, H1 F10, E11, F9, E10, D12, C11, B12, A11 MDATA0-7
I/O
Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bidirectional bus. MD/C, MR/W, and MSTRB determine the mode and data type transferred across the MDATA bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for read operations. Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7 are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0). Power Supply (+3.3V 300mV) Ground No Connect
D4, B2, B3, A3, C4, D5, A4, E5 A1, A8, E6, F8, G1, G8, H5, H8, J7, K9 B1, B8, D11, F3, F4, G2, J3, K8, L4, L11
OFRM1-7 OFRM0 VCC VSS
I/O
Power Power ____
A2, A7, A10, A12, B4, C1, NC C2, C3, C6, C7, C12, D1, D2, D3, D6, D7, D9, D10, E1, E2, E3, E4, E7, E8, E9, E12, F1, F2, F5, F6, F11, F12, G3, G4, G9, G10, G11, G12, H3, H9, H10, H11, H12, J2, J9, J11, K1, K5, K12, L1, L2, L5, L6, L7, L10, M1, M2, M7, M10, M11
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Absolute Maximum Ratings
Symbol VTERM2 TBIAS TSTG IOUT Rating1 Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +3.9 -55 to +125 -55 to +125 50 V C C mA Unit
Recommended DC Operating Conditions
Symbol VCC VSS VIH VIL
1.
Parameter Supply Voltage Ground Input Low Voltage
Min. 3.0 0 -0.51,3
Typ. 3.3 0 ____ ____ 0
Max. 3.6 VCC+0.3V1, 2 0.8
Unit V V V V
Input High Voltage 2.0
1. Stresses greater than those listed in this table may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period of VTERM Vcc + 0.3V.
VTERM must not exceed Vcc + 0.3V or Vss - 0.3V. 2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period of VTERM Vcc + 0.3V. 3. VIL -1.5V for pulse width less than 10ns.
(TA 1.0MHz Capacitance (TA = +25C, f = 1.0MHz) TQFP Only
Symbol CIN COUT3
1.
Parameter1 Input Capacitance Output Capacitance
Conditions2 VIN = 3dV VOUT = 3dV
Max. 9 10
Unit pF pF
Maximum Operating Temperature and Supply Voltage
Grade Industrial
1.
Ambient Temperature -40C to +85C
1
GND 0V 0V
Vcc 3.3V 0.3V 3.3V 0.3V
Commercial 0C to +70C
This is the parameter TA.
These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (Vcc = 3.3V 0.3V)
Symbol |ILI| |ILO|1 VOL VOH
1.
Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
Test Conditions Vcc = 3.6V, VIN = 0V to Vcc RESETI = VIH, VOUT = 0V to Vcc IOL = +4mA IOH = -4mA
77V500S Min ___ ___ ___ 2.4 Max 10 10 0.4 ___ A A V V
Unit
For MDATA, IOD, and OFRM pins only.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC (VCC = 3.3V 0.3V)
Symbol ICC ICCR
1.
Parameter Operating Current Reset Current
Test Conditions Vcc = 3.6V, RESETI = VIL, f = fMAX1 Vcc = 3.6V, RESETI = VIH, f = fMAX1
77V500S25PFI Min 130 150 Max 200 325 Min 130 150
77V500S25PF Max 175 300
Unit mA mA
At f = fmax SCLK is cycling at maximum frequency and all inputs are cycling at 1/tCYC1, using AC input levels of VSS to 3.0V.
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load VSS to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2
3.3V
3.3V
590 DATAOUT 435 50pF DATAOUT 435
590
5pF*
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Figure 1 AC Output Test Load
Figure 2 Output Test Load (for High-Impedance parameters) *Including scope and jig. April 11, 2001
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IDT77V500
AC Electrical Characteristics Over the Operating Temperature Range (Vcc = 3.3V 0.3V)
Symbol tCYC tCH tCL tR tF tMCYC tMCH tMCL tSM tHM tSMRW tHMRW tSMD tHMD tSCRC tHCRC tSIO tHIO tOFP tCDC tDCC tCDS tDCS tCDIO tDCIO tAMD tOHMD tCDOF tDCOF tRSI tRSO tCDR tCKHZ tCKLZ tCYC3 tCH3 tCL3 tCYC2 tCH2 tCL2
1.
Parameter System Clock Cycle Time System Clock High Time System Clock Low Time Clock Rise Time Clock Fall Time Manager Clock Cycle Time Manager Clock High Time Manager Clock Low Time MD/C Setup Time to MSTRB High MD/C Hold Time after MSTRB High MR/W Setup Time to MSTRB High MR/W Hold Time after MSTRB High MDATA Setup Time to MSTRB High MDATA Hold Time after MSTRB High CRCERR Setup Time to SCLK High CRCERR Hold Time after SCLK High IOD Setup Time to SCLK High IOD Hold Time after SCLK High OFRM High Pulse Width SCLK to CMD Valid CMD Output Hold after SCLK High SCLK to SFRM Valid SFRM Output Hold after SCLK High SCLK to IOD Valid IOD Output Hold after SCLK High MSTRB Low to MDATA Valid MDATA Output Hold after MSTRB High SCLK to OFRM/CBUS Valid OFRM/CBUS Output Hold after SCLK High RESETI High Pulse Width1 RESETO High after RESETI High SCLK to RESETO Valid SCLK High to Output High-Z2 SCLK High to Output Low-Z2 CBRCLK3 Clock Cycle Time3 CBRCLK3 Clock High Time3 CBRCLK3 Clock Low Time3 CBRCLK2 Clock Cycle Time3 CBRCLK2 Clock High Time3 CBRCLK2 Clock Low Time3
77V500S25 Com'l & Ind Min. 25 10 10 -- -- 25 6 19 10 2 10 2 10 2 5 2 5 2 5 -- 2 -- 2 -- 2 -- 2 -- 2 8 -- -- -- 2 3 1.2 1.2 3 1.2 1.2 Max. -- -- -- 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18 -- 18 -- 18 -- 18 -- 18 -- -- 2 18 10 -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC tCYC ns ns ns tCYC tCYC tCYC tCYC tCYC tCYC
RESETI must be held High for 8 SCLK cycles. After RESETI transitions Low, 8191 cycles are required before the Status Acknowledge bits will indicate that the internal reset process in complete. 2. Transition is measured +/-200mV from Low or High impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 3. Cycle units insure that the SCLK recognizes the state of CBRCLK.
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IDT77V500
Control Interface Timing Waveform
tCYC tCH SCLK tCDC CMD0-5
GET 1 STATUS GET STATUS
This waveform describes the command interaction across the IOD Bus to the IDT77V400 Switching Memory.
tCL
tDCC
GET HEADER ISAM
tCDIO
STORE ISAM
tCDIO
PUT HEADER [ AVAILABLE FOR NEXT COMMAND ]
tSIO IOD0-31 CRCERR
STATUS 1 STATUS
tHIO
tDCIO
Cell Addr
tDCIO
Output New Header
Input Old Header
Output -
[ CRC ERROR = LOW ]
tSCRC tHCRC
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1
The result of this GET STATUS command is that an ISAM is full and ready to be stored to the Cell Memory of the IDT77V400.
Control Interface Commands(1)
Command Bus Bit (CMD5:0) Command GHIx GST GER STEx LDOx PHE PHEC REF LDC OHE OHEC
1. 2.
1
Command Description Get Header from ISAMx2 Get ISAM Status Register Bits Get Error Register Bits Store Cell in ISAMx2 and Edit Buffer in Memory Load Cell from Memory into OSAMx2 Put new Header in Edit Buffer Put new Header and new CRC byte in Edit Buffer Refresh Cell Memory Load Configuration Register Put new Header in Output Edit Register Put new Header and new CRC byte in Output Edit Register
MSb 5 0 0 0 1 1 1 1 0 1 1 1 4 0 1 1 0 1 1 1 1 1 1 1 3 1 0 0 0 0 1 1 0 1 1 1 2 n3 0 1 n3 n3 1 1 1 0 1 0 1 n3 1 1 n3 n3 0 0 1 1 1 0
LSb 0 n3 0 0 n3 n3 0 1 1 0 0 1
CMD bus commands not defined in this table are undefined and are not implemented by the IDT77V500. "x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively). 3. "n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
SFRM, CBUS, and OFRM Timing Waveforms
SCLK tOFP
OFRM tCDOF tDCOF
OFRM/CBUS
1
tCDS
tDCS
SFRM 1OFRM1-7 become
CBUS1-7 (Outputs) during cell bus operations to arbitrate between multiple IDT77V500's.
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Manager Commands
Command1 WRSL STAT LDCFG SUP INT SEL START CBR PARM
1.
Command Name Write Service Link Memory Read IDT77V500 status
Command Description Write into Service Link Memory to initialize scheduled service lists. Reads the internal status of the IDT77V500. Available information includes various error registers and counts.
Code (in Hex) 03 07 08
Load IDT77V400 Configuration Bits Passes configuration information to the IDT77V400. Call setup Initialize IDT77V500 Select a IDT77V500 End of IDT77V500 Initialization Set up a CBR Scheduler Set Parameters
Writes the appropriate information into an entry of the Per VC Memory to perform the 09 call setup function. Initializes the internal configuration registers of the IDT77V500. Selects the IDT77V500 to be enabled in a multiple device configuration. Sets the IDT77V500 into an enabled state after it has been initialized. Sets up a selected output service list in the Constant Bit Rate (CBR) mode. Sets various parameters in the IDT77V500, including the CLP low water mark, the EFCI low water mark, and the EPD low water mark. 0A 0B 0C 0D 0E
Manager Command codes not defined in this table are not to be used.
Manager Bus Read Timing Waveform
tMCH tMCYC tMCL
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined by the state of the MD/C pin.
1
M S TR B MD/C tSM tSMRW MR/W tSMD MDATA tHMD ADDRIN Write last 8 ADDR bits CMDIN Write CycleRead Command tAMD tOHMD DATAOUT
2
tHM tHMRW
tSM tSMRW
tOHMD tAMD DATAOUT Acknowledge Read DATAOUT
3
ADDRIN Write first 8 ADDR bits
DATAOUT Read Byte 0
DATAOUT
4
Acknowledge Read
Acknowledge Read - Valid Command Acknowledge
Read Byte 1
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The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is available to be read one asynchronous tAMD time after the falling edge of MSTRB if MR/W is High. 2 After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the IDT77V500 must support. 3 A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register). 4 Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used.
1
Manager Bus Write Timing Waveform
tMCH M S TR B
T0
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined by the state of the MD/C pin.
tMCYC tMCL
2
T12
tSM MD/C
tHM
tSM
tSMRW tHMRW MR/W tSMD tHMD MDATA
1
tSMRW
tAMD DATAIN CMDIN DATAOUT Acknowledge Read
tOHMD DATAOUT
3
DATAIN
DATAOUT Acknowledge Read
DATAOUT
4
Write Data Byte 0
Write Data Byte 12
Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first MSTRB of this write waveform. 2The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. The data placed on the MDATA pins is determined by the state of the MD/C pin. 3 After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the IDT77V500 must support. 4 A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
1
Write CycleWrite Command
Acknowledge Read
Acknowledge Read - Valid Command Acknowledge
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IDT77V500
CBR Functional Description
The Constant Bit Rate (CBR) functionality of the IDT77V500 provides both the opportunity for scheduling priority traffic at a regular interval and traffic shaping capability. Two external CBR clocks, CBRCLK3 and CBRCLK2, are available and associated with Output Priority 3 (Highest Priority) and Priority 2 respectively. Calls assigned to a particular CBR VC in the IDT77V500 Per VC Table are linked together in a CBR Per VC list by output, so that a cell from each VC of a particular CBR Per VC list are serviced on each cycle through the list. The CBR Per VC List is identified by both the output and CBR priority on that output; for example, OPyCBRx VC list represents Output y (Output number 0-7) and CBR priority x (CBR priority 3 or 2). Figure 3 is an example of an OPyCBRx VC List with four VCs in the list: 100 (the first entry in the list), 200, 300 and 400. The arrows indicate the linking sequence in this VC List. Figure 3 will be used with the CBR Clock Functional Waveforms to illustrate two basic functional implementations using the CBR Clocks. CBR Clock Functional Waveform Example 1 uses the CBR clocks to frame execution of the OPyCBRx VC List. A cell from a specific VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx. The cell will then be transmitted when output y is available and other previously scheduled Input and Output ports of the IDT77V400 have been serviced. This delay can be as long as 65 SCLK cycles maximum for each cell in the Service Class 3 CBR VC List, although it will typically be significantly less. The Service Class 2 delay can be larger if there is higher priority traffic to be transmitted. This delay needs to be taken into account, as the next cell in the OPyCBRx VC List will not be scheduled until the previous cell in the list has been serviced. Thus enough CBRCLKx pulses need to be provided to make sure all potential cells in the OPyCBRx VC List are scheduled. This waveform illustrates the ideal case of each cell being immediately transmitted after scheduling, enabling the scheduling and transmission of the next cell in the OPyCBRxVC List on the next SCLK rising edge. CBRCLKx HIGH for eight SCLK cycles or more tells the controller that
the pointer should be moved back to the top of the CBR VC List if all the VCs in the list have been serviced. Thus the user can establish a frame duration and be assured that a cell from each VC in the OPyCBRx VC List is transmitted in each frame time. Sub lists can also be established within the CBR VC List so that a particular VC could be weighted to ship more cells per frame than the others. Example 2 illustrates using very slow CBR clocks (tCHx greater than or equal to 8 SCLKs) to shape traffic in a VBR form of implementation. A cell from a VC on the OPyCBRx VC List is again scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx, but since tCHx is HIGH for more than eight SCLKs, there is more direct control over the exact time in which each cell of the VC List is scheduled. The single cell will then be transmitted when the output is available and other previously scheduled Input and Output ports of the IDT77V400 have been serviced (there is again the potential delay based on other traffic passing through the IDT77V400). The IDT77V500 will service all of the VCs in the OPyCBRx VC List because the count will prevent the pointer from returning to the top of the CBR VC List until all VCs on the list with cells have been serviced. The user can thus more closely manage the transmission of cells with this slower CBR clock rate because it is more directly related to individual CBRCLKx High-to-Low transitions.
Beginning
100 200 300
End
400
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Figure 3 OPyBRx VC Example
CBR Clock Parameters
"x" for this waveform represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3).
tCYCx tCLx tCHx
CBRCLKx
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IDT77V500
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation (Fast CBRCLK with Frame Timing)
This example shows the procedure recommended for use of direct CBR scheduling. "x" for this waveform represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3) ("y" represents the specific output (0-7)). The OPyCBRx VC List for this example is defined in Figure 3.
SCLK
1 2 3 100 200 300 400 100 200 300 400 1 2
CBRCLKx
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1 2 3
A cell from a VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx if the previous VC has completed internal processing. This example shows four VCs in the OPyCBRx VC List. The number of VCs in the OPxCBRx VC List may be as large as 8192.
The period between reinitiation of the OPyCBRx VC List defines the frame size; that is, the amount of time between starting the transmissions from the top of the OPyCBRx VC List. CBRCLKx must be HIGH for eight clocks or more to reinitiate the transmission sequence at the start of the OPyCBRx VC List.
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation CHx (tCH (tCHx > 8 SCLK)
This example shows the use of a slower CBRCLK (tCHx > 8 SCLK) to provide VBR/CBR traffic shaping. For this waveform "x" represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3). ("y" represents the specific output (0-7)) The OPyCBRx VC List for this example is defined in Figure 3.
SCLK
1
CBRCLKx
100
2 200 300
see cont'd waveform
cont'd waveform
400
3 100
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1 2 3
A cell from a VC on the OPyCBRx VC List is scheduled on each rising edge of SCLK after a falling edge of CBRCLKx. tCHx > 8 SCLK so that a cell is scheduled after each falling edge of CBRCLKx. The pointer has moved back to the beginning of the OPyCBRx VC List.
Reset Waveforms
1 SCLK tRSI 1 2 7 8 1 2 8190 8191 1 2
RESETI 2 clock cycles max.
2
RESETO
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1RESETI must be held HIGH for 8 SCLK cycles.
When RESETI goes Low again 8191 cycles are used prior to the Status Acknowledge bits showing the internal reset process is com-
plete.
2
This delay should typically be much less than two SCLK cycles. RESETO remains High until START Command is received from the Call Setup Manager.
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IDT77V500
77V500 Package Drawing -- 100-pin TQFP
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IDT77V500
77V500 Package Drawing -- 100-pin TQFP (Page Two)
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IDT77V500
77V500 Package Drawing -- 144-ball BGA
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IDT77V500
77V500 Package Drawing
-- 144-ball (Page Two)
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IDT77V500
Datasheet Document History
3/1/99: Updated to new format. Added Industrial Specifications. Added S25 Speed Grade. Pg. 3 Pg. 4 Pg. 5 Pg. 10 Pg. 14 12/11/00: Package Diagram notes added for clarification. Pin description table descriptions corrected. OFRM and Vss pin number corrections made. VTERM in Maximum ratings table reduced to 3.9V. Manager Bus Sequence Waveforms on page 9 and page 10 and their notes modified for clarity. Updated Ordering Information for S156 speed grade and Industrial temperature product. Added Preliminary Datasheet definition and Datasheet Document History. Moved to final. Updated general format and SwitchStar logo. Pg. 6 Pg. 8 Pg. 10 Pg. 11 Pg. 12 1/30/01: 4/11/01: Corrected tDCC, tDCS, tDCIO, tOHMD, and tDCOF test limits to minimum values instead of maximum values. Clarified OFRM signal on SFRM, CBUS, and OFRM timing waveforms. Clarified CBR delays in text. Clarified SCLK timing in CBR Clock Functional Waveform Example 1 and added information to footnote 1. Corrected package designator to PN100-1. Updated Tech Support phone number. Added BGA package to pages 1, 2, 3, 4,5, and 12. Deleted S27 speed grade on pages 8 and 15. Added 100-pin TQFP and 144-ball BGA package drawings.
Ordering Information
IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PF BC
100-pin TQFP (PN100-1) 144-Ball BGA (BC144-1)
,
25
Commercial & Industrial
System Clock Period in ns
S
Standard Power
77V500 ATM Cell Based Switch Controller
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CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
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for Tech Support: switchstarhelp@idt.com phone: 408-492-8208
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
April 11, 2001

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